The present invention relates generally to semiconductor devices, and more specifically, to a self-limited crack etching process that forms a semiconductor device that is less susceptible to short circuits.
Piezoelectric transistors (PETs) include a piezoelectric element (PE) that may be displaced to modulate the resistance of a piezoresistive (PR) element. The materials used to create a PET pose challenges in formation of the PET. One such challenge is forming a PET structure including a first PET device that requires sputtering through a metal gate layer when forming the first device, while also including a second PET device where sputtering through the metal gate layer and electrical shorting one the sidewall of the piezoelectric material is undesirable.
To prevent electrical shorting caused by metal re-sputtering from forming on the second PET device, current fabrication processes typically use multiple masks and etching processes to isolate the PE material of the second PET device from re-sputtering that may occur when etching the first PET device. However, the additional masks and etching process increase overall costs and resource consumption.
Another attempt to prevent sputtered metal residue from forming on the piezoelectric material of the second device is to form the metal gate material from specific materials with a low tendency to re-sputter and/or are non-conductive after undergoing a sputtering process. This solution, however, may limit the overall application of the piezoelectric material according to the type of material used form the gate metal layer.